There are traditionally two basic types of input/output (I/O) used within computer systems--interrupt driven and direct memory access (DMA). Each of these types of I/O has its advantages and disadvantages, both in terms of performance and cost. Interrupt driven I/O interrupts the main processor each time some amount of data is ready to be transferred, and device driver software running in the processor performs the data transfer, so the processor is always in control of the I/O bus. With DMA I/O, the peripheral device becomes the bus master for the computer system I/O bus and performs data transfer directly into or out of the computer system memory. The peripheral device may obtain the bus, transfer some data, and give up the bus many times during a complete I/O operation. At any time many I/O devices, as well as the processor, may want to become the bus master, so an arbitration method is always needed to select one of the devices as the bus master.
A typical central bus arbitration scheme consists of an arbitration circuit with a grant and request signal for each bus device capable of mastering a transaction on the bus. That is, for each bus device that is capable of becoming a bus master device. This methods works well, but it requires the arbitration circuit to anticipate all future expansion on the bus and provide arbitration signals to support that expansion, thus it requires signals for each device that may ever be connected to the bus. This adds cost to the circuit by forcing it to support arbitration signals that are not necessary in an entry level configuration of the circuit. It also adds cost by increasing the size and complexity of the arbitration circuit and using extra integrated circuit pins unnecessarily. This traditional method also runs the risk of underestimating the future expansion needs so it may limit the ability to meet future requirements.
The IBM personal computer uses the Intel 8237A DMA chip to implement the bus arbitration method for the personal computer bus, and to perform the direct memory access I/O operation for a device. The 8237A chip has four DMA channels, each of which can perform DMA I/O for a peripheral device. In addition, through cascading, separate 8237A chips can be connected to the original 8237A chip to allow expansion up to many devices. Thus, in the smallest entry level system, four different devices are allowed to become bus master, when perhaps only one or two will actually use that capability. Further, the cascading mechanism occupies one of the DMA channels for each cascaded DMA chip, and the DMA channel used for the cascaded DMA chip must be specially programmed to recognize that it is being used for cascading. This places additional limits on the software of the computer system, and requires that the software be specially configured for each different DMA configuration for a computer system. Thus, as in the system described above, this system suffers from adding cost to entry level machines, while placing software limitations and requirements on the computer system.
There is need in the art then for a system that provides for a very small number of devices that can become bus masters to accommodate entry level machines, while having unlimited expandability for fully implemented machines. There is a further need for such a system that requires no programming to implement cascading of the bus arbitration circuit. The present invention meets these and other needs in the art.